SensL’s HRM-TDC is a portable, highly functional timing system providing flexible, easy-to-use timing functions. The HRM-TDC has four channels, each with 27ps timing resolution and a maximum data rate of 4.5MHz over USB to the host computer. The system also comes equipped with 16 general-purpose, user-configurable I/O ports and a programmable TTL clock output.
The HRM-TDC module architecture combines a high performance timing module with a high end FPGA, on-board memory and a high speed USB 2.0 interface. The FPGA is the heart of the system and controls all aspects of operation in addition to performing commands from the external host computer. It uses a proprietary communication protocol for communication with the host PC running either the SensL Integrated Environment (SIE), or the users own application built using the SensL DLL. The SIE, DLL and LabView drivers are provided for the system.